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Digital design
- RTL LOGIC DESCRIPTION
- RTL CODE ANALYSIS
- DFT DESIGN
- SOC ARCHITECTURE
Digital and Mixed signal verification
- VERIFICATION PLAN DEFINITION
- UVM BASED FUNCTIONAL VERIFICATION
- ASSERTIONS BASED VERIFICATION
- CODE COVERAGE ANALYSIS
Gate-level flow
- Logic synthesis
- STA analysis
- Scan chain insertion
- Scan patterns generation and simulation
FPGA based prototyping
- LOGIC SYNTHESIS FOR THE FPGA
- TESTING AND DEBUGGING
- EMBEDDED PROGRAMMING
